In a typical inverter device, a switching element is used to drive a load. Moreover, a high-withstand-voltage IC is used to drive control the switching of the switching element. A negative surge, however, is generated when the switching element performs switching. The negative surge is generated due to a variation in current per unit time (di/dt) and inductance of the wiring. Patent Document 1 discloses a technology for suppressing the generation of the negative surge. Specifically, Patent Document 1 teaches to connect a clamp diode between a low-voltage reference terminal and a high-voltage reference terminal of the high-withstand-voltage IC.
A negative voltage generated due to a small inductance resulting from a chip pattern, wiring, and the like, is the prime cause of the breakdown of the high-withstand-voltage IC. In the technology disclosed in Patent Document 1, the negative voltage is clamped by using the clamp diode to prevent the breakdown of the high-withstand-voltage IC.
On the other hand, Patent Document 2 teaches to provide a voltage divider circuit (resistance element) in series with the clamp diode in the configuration disclosed in Patent Document 1.
Not all the negative voltage, however, can be suppressed with the clamp diode. In the technology disclosed in Patent Document 2, the negative voltage, which cannot be suppressed with the clamp diode, is divided by using the clamp diode and the resistance element of the voltage divider circuit to reduce the level of the negative voltage applied to the high-withstand-voltage IC.
[Patent Document 1] Japanese Patent Application Laid-open No. 10-42575
[Patent Document 2] Japanese Patent No. 3577478